There are many circuits and systems that utilize a periodic digital signal in which the duty cycle of the signal is an important parameter. For example, in digital electronic systems, synchronization is a very important element, that is, the clock signal keeps various segments of the system in synchrony for proper operation. In many instances, a main clock generates the clock signal but the signal must travel to different parts of the system or must be processed by different components having different delay characteristics. In high speed digital systems, the skew among the clock signals must be properly handled. The skew (delay) between two clock signals of the same clock frequency can be easily measured by calculating the duty cycle of a digital signal generated by combining the two clock signals.
The duty cycle is also important in other areas. Circuits and systems employing pulse width modulation techniques may include a feedback loop based on the duty cycle of a signal. The duty cycle, of course, is commonly defined as the percentage of time over one cycle that a digital signal is in a positive or active state, usually expressed as a percent.
U.S. Pat. No. 5,210,444, issued May 11, 1993 (Johnson), describes a duty cycle meter for measuring the duty cycle of a digital signal of a known frequency. It uses a local oscillator which produces pulses at a frequency higher than that of the digital signal. It counts the number of oscillator pulses during the period when the digital signal is at the active state (high level). In a specific embodiment the oscillator frequency is a power of ten multiple of the digital signal frequency. In this case the number of oscillator pulses is a direct indication of the duty cycle. The technique described therein, however, requires a local oscillator which must operate faster than the digital signal to be measured. For high speed digital systems this may not be possible and would also give bad resolution.